1. Technical Field
This invention generally relates to testing of integrated circuits, and more specifically relates to built-in self-test circuits and methods implemented on an integrated circuit chip to test the function of a portion of the integrated circuit, such as a memory array.
2. Background Art
Advances in integrated circuits have enhanced the ability to integrate increasingly more circuits on a single chip. As the circuit complexity on a chip increases, so does the need to thoroughly test the circuits. However, many of these circuits have few or no connections that are accessible to external test equipment, making the direct testing of these circuits by external equipment very difficult or impossible altogether. A general solution to the problem of testing integrated circuits is to embed test circuitry on the chip itself, commonly known as Array Built-In Self-Test (ABIST) circuits. ABIST circuits typically test the functionality of an on-chip circuit and provide a failure indication if the circuit is not functioning properly.
As the number of circuits integrated onto a single chip increases, the complexity and sophistication of on-chip self-test circuits also increases. A variety of different types of self-test circuits are known for different applications. One such type of self-test circuit generates random data patterns to apply to the memory array. Examples of random data self-test circuits include: U.S. Pat. No. 5,331,643 "Self-Testing Logic with Embedded Arrays" (issued Jul. 19, 1994 to Smith and assigned to IBM); U.S. Pat. No. 5,301,199 "Built-In Self Test Circuit" (issued Apr. 5, 1994 to Ikenega el al. and assigned to Nippon Telegraph and Telephone Corp.); U.S. Pat. No. 5,138,619 "Built-In Self Test for Integrated Circuit Memory" (issued Aug. 11, 1992 to Fasang et al. and assigned to National Semiconductor Corp.); and U.S. Pat. No. 5,006,787 "Self-Testing Circuitry for VLSI Units" (issued Apr. 9, 1991 to Katircioglu et al. and assigned to Unisys Corp.). All the patents listed above are incorporate herein by reference.
Self-test circuits that generate random data, such as those listed above, cannot be used for deterministic testing of the memory array, i.e., to test the array with a defined sequence of data. In addition, random data cannot place the memory array in a known state, which is required, for example, during Static Voltage Screen (SVS) testing. However, other self-test circuits are known which generate programmable data. For example, U.S. Pat. No. 5,224,101 "Micro-Coded Self-Test Apparatus for a Memory Array" (issued Jun. 29, 1993 to Popyack, Jr. and assigned to the United States) discloses a self-test circuit that uses a microcode sequencer to determine the testing algorithm from the contents of a Read Only Memory (OM), and is incorporated herein by reference. Once the algorithm has been programmed into the ROM, however, the testing algorithm is fixed, and cannot be re-programed for different test parameters. U.S. Pat. No. 5,301,156 "Configurable Self-Test for Embedded Rams" (issued Apr. 5, 1994 to Talley and assigned to Hewlett Packard Co.) discloses a self-test circuit that has a serial scan path that passes through the address and data portions of the circuit to allow scanning a test vector into the self-test circuit, and to allow scanning the results of the test out of the self-test circuit. While the data may be dynamically changed by scanning in a new test vector, this process of scanning in data each time the data changes during the test is very time-consuming, making the testing of large memory arrays excessively slow and impractical. The two patents discussed above are incorporated herein by reference.
One example of an improved ABIST circuit is disclosed in U.S. Pat. No. 5,173,906 "Built-In Self Test for Integrated Circuits" (issued Dec. 22, 1992 to Dreibelbis et al.), which is also incorporated herein by reference. The ABIST circuit disclosed by Dreibelbis et al. provides five fixed patterns and one programmable (PG) pattern for testing a memory array. The PG pattern provides for greater flexibility in testing a circuit such as a memory array by providing configuration variables that determine the specific programming pattern and sequence to be applied by the ABIST circuit to the cells within the memory array.
The PG pattern generator within the ABIST circuit of Dreibelbis et al. initializes appropriate configuration variables using scan chain initialization, a technique that is known in the art. Each pattern typically consists of one or more subcycles: RC1, RC2, WC, RC3, and RC4. A subcycle defines the R/W operation performed on the memory array under test as its entire address space is ascended or descended by the ABIST state machine's address counter. When the last address is reached, a new subcycle is commenced and the array's address space is again traversed. The WC subcycle is a blanket write cycle, wherein every cell within the memory array is written with the same data, either a zero or a one. During the RC1, RC2, RC3 and RC4 subcycles, the cells within the memory array may be read or written. It is typically during the RC3 and RC4 subcycles that the programmable operations are performed.
The ABIST circuit of Dreibelbis et al. typically executes each of the five fixed patterns along with the programmable pattern in sequential fashion. Each of the six test patterns have a code corresponding to the output of a three bit binary counter. The starting point for the test sequence may be selected by loading in the appropriate codes during scan-in initialization. A looping feature, when enabled, causes the ABIST circuit to loop on a given pattern, repeating all the subcycles for that pattern.
The ABIST circuit disclosed by Dreibelbis et al. was a significant advancement over the existing prior art at the time by providing the capability to continue looping through a pattern rather than having the ABIST circuit stop at the end of the test. However this looping capability requires the ABIST to repeat all the subcycles in a given pattern, which may be undesirable in certain circumstances.
For Static Voltage Screen (SVS) testing, it is generally desirable to put the memory array in a known state, preferably checkerboard, for a given period of time, followed by a different known state, preferably an inverse checkerboard, for a second period of time. The checkerboard/inverse checkerboard sequence is needed for SVS testing, yet the ABIST circuit of Dreibelbis et al. does not allow for stopping the ABIST when the memory array is in a known state.
The need for placing a memory array in a known state is complicated by the presence of several memory arrays of different size, each of which have a corresponding ABIST circuit. While the circuit of Dreibelbis et al. could be used for each ABIST to loop the checkerboard pattern, the steps which the subcycles perform during the checkerboard pattern are:
1) Write a checkerboard pattern
2) Read the checkerboard pattern
3) Write an inverse checkerboard pattern
4) Read the inverse checkerboard pattern
If there are several memory arrays that are different sizes, the continuous looping of this checkerboard pattern by each ABIST will result in both the true and inverse checkerboard being written repeatedly. Thus, if the ABIST is stopped, there is no way of assuring that all the memory arrays are in a known state, since a portion of a particular memory array may be in inverse checkerboard state while the rest is in checkerboard state.
Furthermore, in situ burn-in testing requires that the circuits in the memory array be exercised repeatedly during the test. One way to exercise the memory array is to continually loop the entire ABIST pattern, as disclosed in Dreibelbis et al. Another desirable method for exercising the circuitry of the memory array during burn-in is to continually loop on one particular subcycle within the ABIST pattern sequence, which is impossible using the ABIST circuit of Dreibelbis et al.
Therefore, there existed a need to provide an ABIST circuit that may be stopped once the memory array is in a known state. This capability is useful, for example, in SVS testing. In addition, there existed a need to provide an ABIST circuit that can repeatedly cycle on a given step (i.e., subcycle within a pattern). This capability is especially useful to exercise the circuitry in the memory array during in situ burn-in testing.